diff options
Diffstat (limited to 'F2024/coe718/labs/lab1/Boards/Keil/MCB1700/Blinky_ULp/RTE')
6 files changed, 2106 insertions, 0 deletions
diff --git a/F2024/coe718/labs/lab1/Boards/Keil/MCB1700/Blinky_ULp/RTE/Device/LPC1768/RTE_Device.h b/F2024/coe718/labs/lab1/Boards/Keil/MCB1700/Blinky_ULp/RTE/Device/LPC1768/RTE_Device.h new file mode 100755 index 0000000..1ac9c01 --- /dev/null +++ b/F2024/coe718/labs/lab1/Boards/Keil/MCB1700/Blinky_ULp/RTE/Device/LPC1768/RTE_Device.h @@ -0,0 +1,1167 @@ +/* ----------------------------------------------------------------------------- + * Copyright (c) 2013-2016 ARM Ltd. + * + * This software is provided 'as-is', without any express or implied warranty. + * In no event will the authors be held liable for any damages arising from + * the use of this software. Permission is granted to anyone to use this + * software for any purpose, including commercial applications, and to alter + * it and redistribute it freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software in + * a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * + * 3. This notice may not be removed or altered from any source distribution. + * + * $Date: 20. April 2016 + * $Revision: V2.4.1 + * + * Project: RTE Device Configuration for NXP LPC17xx + * -------------------------------------------------------------------------- */ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +#ifndef __RTE_DEVICE_H +#define __RTE_DEVICE_H + + +// <e> USB Controller [Driver_USBD and Driver_USBH] +// <i> Configuration settings for Driver_USBD in component ::Drivers:USB Device +// <i> Configuration settings for Driver_USBH in component ::Drivers:USB Host +#define RTE_USB_USB0 0 + +// <h> Pin Configuration +// <o> USB_PPWR (Host) <0=>Not used <1=>P1_19 +// <i> VBUS drive signal (towards external charge pump or power management unit). +#define RTE_USB_PPWR_ID 1 +#if (RTE_USB_PPWR_ID == 0) + #define RTE_USB_PPWR_PIN_EN 0 +#elif (RTE_USB_PPWR_ID == 1) + #define RTE_USB_PPWR_PIN_EN 1 +#else + #error "Invalid RTE_USB_PPWR Pin Configuration!" +#endif + +// <o> USB_PWRD (Host) <0=>Not used <1=>P1_22 +// <i> Power Status for USB port. +#define RTE_USB_PWRD_ID 1 +#if (RTE_USB_PWRD_ID == 0) + #define RTE_USB_PWRD_PIN_EN 0 +#elif (RTE_USB_PWRD_ID == 1) + #define RTE_USB_PWRD_PIN_EN 1 +#else + #error "Invalid RTE_USB_PWRD Pin Configuration!" +#endif + +// <o> USB_OVRCR (Host) <0=>Not used <1=>P1_27 +// <i> Port power fault signal indicating overcurrent condition. +// <i> This signal monitors over-current on the USB bus +// (external circuitry required to detect over-current condition). +#define RTE_USB_OVRCR_ID 0 +#if (RTE_USB_OVRCR_ID == 0) + #define RTE_USB_OVRCR_PIN_EN 0 +#elif (RTE_USB_OVRCR_ID == 1) + #define RTE_USB_OVRCR_PIN_EN 1 +#else + #error "Invalid RTE_USB_OVRCR Pin Configuration!" +#endif + +// <o> USB_CONNECT (Device) <0=>Not used <1=>P2_9 +// <i> SoftConnect control signal +#define RTE_USB_CONNECT_ID 1 +#if (RTE_USB_CONNECT_ID == 0) + #define RTE_USB_CONNECT_PIN_EN 0 +#elif (RTE_USB_CONNECT_ID == 1) + #define RTE_USB_CONNECT_PIN_EN 1 +#else + #error "Invalid RTE_USB_CONNECT Pin Configuration!" +#endif + +// <o> USB_VBUS (Device) <0=>Not used <1=>P1_30 +// <i> VBUS status input. +// <i> When this function is not enabled via its corresponding PINSEL register, it is driven HIGH internally. +#define RTE_USB_VBUS_ID 1 +#if (RTE_USB_VBUS_ID == 0) + #define RTE_USB_VBUS_PIN_EN 0 +#elif (RTE_USB_VBUS_ID == 1) + #define RTE_USB_VBUS_PIN_EN 1 +#else + #error "Invalid RTE_USB_VBUS Pin Configuration!" +#endif + +// <o> USB_UP_LED <0=>Not used <1=>P1_18 +// <i> GoodLink LED control signal. +#define RTE_USB_UP_LED_ID 1 +#if (RTE_USB_UP_LED_ID == 0) + #define RTE_USB_UP_LED_PIN_EN 0 +#elif (RTE_USB_UP_LED_ID == 1) + #define RTE_USB_UP_LED_PIN_EN 1 +#else + #error "Invalid RTE_USB_UP_LED Pin Configuration!" +#endif + +// </h> Pin Configuration +// </e> USB Controller [Driver_USBD and Driver_USBH] + + +// <e> ENET (Ethernet Interface) [Driver_ETH_MAC0] +// <i> Configuration settings for Driver_ETH_MAC0 in component ::Drivers:Ethernet MAC +#define RTE_ENET 0 + + +// <h> RMII (Reduced Media Independent Interface) +#define RTE_ENET_RMII 1 + +// <o> ENET_TXD0 Pin <0=>P1_0 +#define RTE_ENET_RMII_TXD0_PORT_ID 0 +#if (RTE_ENET_RMII_TXD0_PORT_ID == 0) +#define RTE_ENET_RMII_TXD0_PORT 1 +#define RTE_ENET_RMII_TXD0_PIN 0 +#define RTE_ENET_RMII_TXD0_FUNC 1 +#else +#error "Invalid ENET_TXD0 Pin Configuration!" +#endif +// <o> ENET_TXD1 Pin <0=>P1_1 +#define RTE_ENET_RMII_TXD1_PORT_ID 0 +#if (RTE_ENET_RMII_TXD1_PORT_ID == 0) +#define RTE_ENET_RMII_TXD1_PORT 1 +#define RTE_ENET_RMII_TXD1_PIN 1 +#define RTE_ENET_RMII_TXD1_FUNC 1 +#else +#error "Invalid ENET_TXD1 Pin Configuration!" +#endif +// <o> ENET_REF_CLK Pin <0=>P1_15 +#define RTE_ENET_RMII_REF_CLK_PORT_ID 0 +#if (RTE_ENET_RMII_REF_CLK_PORT_ID == 0) +#define RTE_ENET_RMII_REF_CLK_PORT 1 +#define RTE_ENET_RMII_REF_CLK_PIN 15 +#define RTE_ENET_RMII_REF_CLK_FUNC 1 +#else +#error "Invalid ENET_REF_CLK Pin Configuration!" +#endif +// <o> ENET_TX_EN Pin <0=>P1_4 +#define RTE_ENET_RMII_TX_EN_PORT_ID 0 +#if (RTE_ENET_RMII_TX_EN_PORT_ID == 0) +#define RTE_ENET_RMII_TX_EN_PORT 1 +#define RTE_ENET_RMII_TX_EN_PIN 4 +#define RTE_ENET_RMII_TX_EN_FUNC 1 +#else +#error "Invalid ENET_TX_EN Pin Configuration!" +#endif +// <o> ENET_CRS Pin <0=>P1_8 +#define RTE_ENET_RMII_CRS_PORT_ID 0 +#if (RTE_ENET_RMII_CRS_PORT_ID == 0) +#define RTE_ENET_RMII_CRS_PORT 1 +#define RTE_ENET_RMII_CRS_PIN 8 +#define RTE_ENET_RMII_CRS_FUNC 1 +#else +#error "Invalid ENET_CRS Pin Configuration!" +#endif +// <o> ENET_RXD0 Pin <0=>P1_9 +#define RTE_ENET_RMII_RXD0_PORT_ID 0 +#if (RTE_ENET_RMII_RXD0_PORT_ID == 0) +#define RTE_ENET_RMII_RXD0_PORT 1 +#define RTE_ENET_RMII_RXD0_PIN 9 +#define RTE_ENET_RMII_RXD0_FUNC 1 +#else +#error "Invalid ENET_RXD0 Pin Configuration!" +#endif +// <o> ENET_RXD1 Pin <0=>P1_10 +#define RTE_ENET_RMII_RXD1_PORT_ID 0 +#if (RTE_ENET_RMII_RXD1_PORT_ID == 0) +#define RTE_ENET_RMII_RXD1_PORT 1 +#define RTE_ENET_RMII_RXD1_PIN 10 +#define RTE_ENET_RMII_RXD1_FUNC 1 +#else +#error "Invalid ENET_RXD1 Pin Configuration!" +#endif +// <o> ENET_RX_ER Pin <0=>P1_14 +#define RTE_ENET_RMII_RX_ER_PORT_ID 0 +#if (RTE_ENET_RMII_RX_ER_PORT_ID == 0) +#define RTE_ENET_RMII_RX_ER_PORT 1 +#define RTE_ENET_RMII_RX_ER_PIN 14 +#define RTE_ENET_RMII_RX_ER_FUNC 1 +#else +#error "Invalid ENET_REF_CLK Pin Configuration!" +#endif +// </h> + +// <h> MIIM (Management Data Interface) +// <o> ENET_MDC Pin <0=>P1_16 <1=>P2_8 +#define RTE_ENET_MDI_MDC_PORT_ID 0 +#if (RTE_ENET_MDI_MDC_PORT_ID == 0) +#define RTE_ENET_MDI_MDC_PORT 1 +#define RTE_ENET_MDI_MDC_PIN 16 +#define RTE_ENET_MDI_MDC_FUNC 1 +#elif (RTE_ENET_MDI_MDC_PORT_ID == 1) +#define RTE_ENET_MDI_MDC_PORT 2 +#define RTE_ENET_MDI_MDC_PIN 8 +#define RTE_ENET_MDI_MDC_FUNC 3 +#else +#error "Invalid ENET_MDC Pin Configuration!" +#endif +// <o> ENET_MDIO Pin <0=>P1_17 <1=>P2_9 +#define RTE_ENET_MDI_MDIO_PORT_ID 0 +#if (RTE_ENET_MDI_MDIO_PORT_ID == 0) +#define RTE_ENET_MDI_MDIO_PORT 1 +#define RTE_ENET_MDI_MDIO_PIN 17 +#define RTE_ENET_MDI_MDIO_FUNC 1 +#elif (RTE_ENET_MDI_MDIO_PORT_ID == 1) +#define RTE_ENET_MDI_MDIO_PORT 2 +#define RTE_ENET_MDI_MDIO_PIN 9 +#define RTE_ENET_MDI_MDIO_FUNC 3 +#else +#error "Invalid ENET_MDIO Pin Configuration!" +#endif +// </h> + +// </e> + + +// <e> I2C0 (Inter-integrated Circuit Interface 0) [Driver_I2C0] +// <i> Configuration settings for Driver_I2C0 in component ::Drivers:I2C +#define RTE_I2C0 0 + +// <o> I2C0_SCL Pin <0=>P0_28 +#define RTE_I2C0_SCL_PORT_ID 0 +#if (RTE_I2C0_SCL_PORT_ID == 0) +#define RTE_I2C0_SCL_PORT 0 +#define RTE_I2C0_SCL_PIN 28 +#define RTE_I2C0_SCL_FUNC 1 +#else +#error "Invalid I2C0_SCL Pin Configuration!" +#endif + +// <o> I2C0_SDA Pin <0=>P0_27 +#define RTE_I2C0_SDA_PORT_ID 0 +#if (RTE_I2C0_SDA_PORT_ID == 0) +#define RTE_I2C0_SDA_PORT 0 +#define RTE_I2C0_SDA_PIN 27 +#define RTE_I2C0_SDA_FUNC 1 +#else +#error "Invalid I2C0_SDA Pin Configuration!" +#endif + +// </e> + + +// <e> I2C1 (Inter-integrated Circuit Interface 1) [Driver_I2C1] +// <i> Configuration settings for Driver_I2C1 in component ::Drivers:I2C +#define RTE_I2C1 0 + +// <o> I2C1_SCL Pin <0=>P0_1 <1=>P0_20 +#define RTE_I2C1_SCL_PORT_ID 0 +#if (RTE_I2C1_SCL_PORT_ID == 0) +#define RTE_I2C1_SCL_PORT 0 +#define RTE_I2C1_SCL_PIN 1 +#define RTE_I2C1_SCL_FUNC 3 +#elif (RTE_I2C1_SCL_PORT_ID == 1) +#define RTE_I2C1_SCL_PORT 0 +#define RTE_I2C1_SCL_PIN 20 +#define RTE_I2C1_SCL_FUNC 3 +#else +#error "Invalid I2C1_SCL Pin Configuration!" +#endif + +// <o> I2C1_SDA Pin <0=>P0_0 <1=>P0_19 +#define RTE_I2C1_SDA_PORT_ID 0 +#if (RTE_I2C1_SDA_PORT_ID == 0) +#define RTE_I2C1_SDA_PORT 0 +#define RTE_I2C1_SDA_PIN 0 +#define RTE_I2C1_SDA_FUNC 3 +#elif (RTE_I2C1_SDA_PORT_ID == 1) +#define RTE_I2C1_SDA_PORT 0 +#define RTE_I2C1_SDA_PIN 19 +#define RTE_I2C1_SDA_FUNC 3 +#else +#error "Invalid I2C1_SDA Pin Configuration!" +#endif + +// </e> + + +// <e> I2C2 (Inter-integrated Circuit Interface 2) [Driver_I2C2] +// <i> Configuration settings for Driver_I2C2 in component ::Drivers:I2C +#define RTE_I2C2 0 + +// <o> I2C2_SCL Pin <0=>P0_11 +#define RTE_I2C2_SCL_PORT_ID 0 +#if (RTE_I2C2_SCL_PORT_ID == 0) +#define RTE_I2C2_SCL_PORT 0 +#define RTE_I2C2_SCL_PIN 11 +#define RTE_I2C2_SCL_FUNC 2 +#else +#error "Invalid I2C2_SCL Pin Configuration!" +#endif + +// <o> I2C2_SDA Pin <0=>P0_10 +#define RTE_I2C2_SDA_PORT_ID 0 +#if (RTE_I2C2_SDA_PORT_ID == 0) +#define RTE_I2C2_SDA_PORT 0 +#define RTE_I2C2_SDA_PIN 10 +#define RTE_I2C2_SDA_FUNC 2 +#else +#error "Invalid I2C2_SDA Pin Configuration!" +#endif + +// </e> + +// <e> UART0 (Universal asynchronous receiver transmitter) +#define RTE_UART0 0 + +// <o> UART0_TX Pin <0=>Not used <1=>P0_2 +// <i> UART0 Serial Output pin +#define RTE_UART0_TX_ID 0 +#if (RTE_UART0_TX_ID == 0) +#define RTE_UART0_TX_PIN_EN 0 +#elif (RTE_UART0_TX_ID == 1) +#define RTE_UART0_TX_PORT 0 +#define RTE_UART0_TX_BIT 2 +#define RTE_UART0_TX_FUNC 1 +#else +#error "Invalid UART0_TX Pin Configuration!" +#endif +#ifndef RTE_UART0_TX_PIN_EN +#define RTE_UART0_TX_PIN_EN 1 +#endif + +// <o> UART0_RX Pin <0=>Not used <1=>P0_3 +// <i> UART0 Serial Input pin +#define RTE_UART0_RX_ID 0 +#if (RTE_UART0_RX_ID == 0) +#define RTE_UART0_RX_PIN_EN 0 +#elif (RTE_UART0_RX_ID == 1) +#define RTE_UART0_RX_PORT 0 +#define RTE_UART0_RX_BIT 3 +#define RTE_UART0_RX_FUNC 1 +#else +#error "Invalid UART0_RX Pin Configuration!" +#endif +#ifndef RTE_UART0_RX_PIN_EN +#define RTE_UART0_RX_PIN_EN 1 +#endif + +// <h> DMA +// <e> Tx +// <o1> Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 +// </e> +#define RTE_UART0_DMA_TX_EN 1 +#define RTE_UART0_DMA_TX_CH 0 +// <e> Rx +// <o1> Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 +// </e> +#define RTE_UART0_DMA_RX_EN 1 +#define RTE_UART0_DMA_RX_CH 1 +// </h> DMA + +// </e> +// <e> UART1 (Universal asynchronous receiver transmitter) +#define RTE_UART1 0 + +// <o> U1_TX Pin <0=>Not used <1=>P0_15 <2=>P2_0 +// <i> UART1 Serial Output pin +#define RTE_UART1_TX_ID 1 +#if (RTE_UART1_TX_ID == 0) +#define RTE_UART1_TX_PIN_EN 0 +#elif (RTE_UART1_TX_ID == 1) +#define RTE_UART1_TX_PORT 0 +#define RTE_UART1_TX_BIT 15 +#define RTE_UART1_TX_FUNC 1 +#elif (RTE_UART1_TX_ID == 2) +#define RTE_UART1_TX_PORT 2 +#define RTE_UART1_TX_BIT 0 +#define RTE_UART1_TX_FUNC 2 +#else +#error "Invalid U1_TX Pin Configuration!" +#endif +#ifndef RTE_UART1_TX_PIN_EN +#define RTE_UART1_TX_PIN_EN 1 +#endif + +// <o> U1_RX Pin <0=>Not used <1=>P0_16 <2=>P2_1 +// <i> UART1 Serial Input pin +#define RTE_UART1_RX_ID 1 +#if (RTE_UART1_RX_ID == 0) +#define RTE_UART1_RX_PIN_EN 0 +#elif (RTE_UART1_RX_ID == 1) +#define RTE_UART1_RX_PORT 0 +#define RTE_UART1_RX_BIT 16 +#define RTE_UART1_RX_FUNC 1 +#elif (RTE_UART1_RX_ID == 2) +#define RTE_UART1_RX_PORT 2 +#define RTE_UART1_RX_BIT 1 +#define RTE_UART1_RX_FUNC 2 +#else +#error "Invalid U1_RX Pin Configuration!" +#endif +#ifndef RTE_UART1_RX_PIN_EN +#define RTE_UART1_RX_PIN_EN 1 +#endif + +// <h> Modem Lines +// <o> CTS <0=>Not used <1=>P0_17 <2=>P2_2 +#define RTE_UART1_CTS_ID 0 +#if (RTE_UART1_CTS_ID == 0) +#define RTE_UART1_CTS_PIN_EN 0 +#elif (RTE_UART1_CTS_ID == 1) +#define RTE_UART1_CTS_PORT 0 +#define RTE_UART1_CTS_BIT 17 +#define RTE_UART1_CTS_FUNC 1 +#elif (RTE_UART1_CTS_ID == 2) +#define RTE_UART1_CTS_PORT 2 +#define RTE_UART1_CTS_BIT 2 +#define RTE_UART1_CTS_FUNC 2 +#else +#error "Invalid U1_CTS Pin Configuration!" +#endif +#ifndef RTE_UART1_CTS_PIN_EN +#define RTE_UART1_CTS_PIN_EN 1 +#endif + +// +// <o> DCD <0=>Not used <1=>P0_18 <2=>P2_3 +#define RTE_UART1_DCD_ID 0 +#if (RTE_UART1_DCD_ID == 0) +#define RTE_UART1_DCD_PIN_EN 0 +#elif (RTE_UART1_DCD_ID == 1) +#define RTE_UART1_DCD_PORT 0 +#define RTE_UART1_DCD_BIT 18 +#define RTE_UART1_DCD_FUNC 1 +#elif (RTE_UART1_DCD_ID == 2) +#define RTE_UART1_DCD_PORT 2 +#define RTE_UART1_DCD_BIT 3 +#define RTE_UART1_DCD_FUNC 2 +#else +#error "Invalid UART1_DCD Pin Configuration!" +#endif +#ifndef RTE_UART1_DCD_PIN_EN +#define RTE_UART1_DCD_PIN_EN 1 +#endif + +// <o> DSR <0=>Not used <1=>P0_19 <2=>P2_4 +#define RTE_UART1_DSR_ID 0 +#if (RTE_UART1_DSR_ID == 0) +#define RTE_UART1_DSR_PIN_EN 0 +#elif (RTE_UART1_DSR_ID == 1) +#define RTE_UART1_DSR_PORT 0 +#define RTE_UART1_DSR_BIT 19 +#define RTE_UART1_DSR_FUNC 1 +#elif (RTE_UART1_DSR_ID == 2) +#define RTE_UART1_DSR_PORT 2 +#define RTE_UART1_DSR_BIT 4 +#define RTE_UART1_DSR_FUNC 2 +#else +#error "Invalid UART1_DSR Pin Configuration!" +#endif +#ifndef RTE_UART1_DSR_PIN_EN +#define RTE_UART1_DSR_PIN_EN 1 +#endif + +// <o> DTR <0=>Not used <1=>P0_20 <2=>P2_5 +#define RTE_UART1_DTR_ID 0 +#if (RTE_UART1_DTR_ID == 0) +#define RTE_UART1_DTR_PIN_EN 0 +#elif (RTE_UART1_DTR_ID == 1) +#define RTE_UART1_DTR_PORT 0 +#define RTE_UART1_DTR_BIT 20 +#define RTE_UART1_DTR_FUNC 1 +#elif (RTE_UART1_DTR_ID == 2) +#define RTE_UART1_DTR_PORT 2 +#define RTE_UART1_DTR_BIT 5 +#define RTE_UART1_DTR_FUNC 2 +#else +#error "Invalid UART1_DTR Pin Configuration!" +#endif +#ifndef RTE_UART1_DTR_PIN_EN +#define RTE_UART1_DTR_PIN_EN 1 +#endif + +// <o> RI <0=>Not used <1=>P0_21 <2=>P2_6 +#define RTE_UART1_RI_ID 0 +#if (RTE_UART1_RI_ID == 0) +#define RTE_UART1_RI_PIN_EN 0 +#elif (RTE_UART1_RI_ID == 1) +#define RTE_UART1_RI_PORT 0 +#define RTE_UART1_RI_BIT 21 +#define RTE_UART1_RI_FUNC 1 +#elif (RTE_UART1_RI_ID == 2) +#define RTE_UART1_RI_PORT 2 +#define RTE_UART1_RI_BIT 6 +#define RTE_UART1_RI_FUNC 2 +#else +#error "Invalid UART1_RI Pin Configuration!" +#endif +#ifndef RTE_UART1_RI_PIN_EN +#define RTE_UART1_RI_PIN_EN 1 +#endif + +// <o> RTS <0=>Not used <1=>P0_22 <2=>P2_7 +#define RTE_UART1_RTS_ID 0 +#if (RTE_UART1_RTS_ID == 0) +#define RTE_UART1_RTS_PIN_EN 0 +#elif (RTE_UART1_RTS_ID == 1) +#define RTE_UART1_RTS_PORT 0 +#define RTE_UART1_RTS_BIT 22 +#define RTE_UART1_RTS_FUNC 1 +#elif (RTE_UART1_RTS_ID == 2) +#define RTE_UART1_RTS_PORT 2 +#define RTE_UART1_RTS_BIT 7 +#define RTE_UART1_RTS_FUNC 2 +#else +#error "Invalid UART1_RTS Pin Configuration!" +#endif +#ifndef RTE_UART1_RTS_PIN_EN +#define RTE_UART1_RTS_PIN_EN 1 +#endif + +// </h> + +// <h> DMA +// <e> Tx +// <o1> Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 +// </e> +#define RTE_UART1_DMA_TX_EN 1 +#define RTE_UART1_DMA_TX_CH 0 +// <e> Rx +// <o1> Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 +// </e> +#define RTE_UART1_DMA_RX_EN 1 +#define RTE_UART1_DMA_RX_CH 1 +// </h> DMA + +// </e> + +// <e> UART2 (Universal asynchronous receiver transmitter) +#define RTE_UART2 0 + +// <o> UART2_TX Pin <0=>Not used <1=>P0_10 <2=>P2_8 +// <i> UART2 Serial Output pin +#define RTE_UART2_TX_ID 0 +#if (RTE_UART2_TX_ID == 0) +#define RTE_UART2_TX_PIN_EN 0 +#elif (RTE_UART2_TX_ID == 1) +#define RTE_UART2_TX_PORT 0 +#define RTE_UART2_TX_BIT 10 +#define RTE_UART2_TX_FUNC 1 +#elif (RTE_UART2_TX_ID == 2) +#define RTE_UART2_TX_PORT 2 +#define RTE_UART2_TX_BIT 8 +#define RTE_UART2_TX_FUNC 2 +#else +#error "Invalid UART2_TX Pin Configuration!" +#endif +#ifndef RTE_UART2_TX_PIN_EN +#define RTE_UART2_TX_PIN_EN 1 +#endif + +// <o> UART2_RX Pin <0=>Not used <1=>P0_11 <2=>P2_9 +// <i> UART2 Serial Input pin +#define RTE_UART2_RX_ID 0 +#if (RTE_UART2_RX_ID == 0) +#define RTE_UART2_RX_PIN_EN 0 +#elif (RTE_UART2_RX_ID == 1) +#define RTE_UART2_RX_PORT 0 +#define RTE_UART2_RX_BIT 11 +#define RTE_UART2_RX_FUNC 1 +#elif (RTE_UART2_RX_ID == 2) +#define RTE_UART2_RX_PORT 2 +#define RTE_UART2_RX_BIT 9 +#define RTE_UART2_RX_FUNC 2 +#else +#error "Invalid UART2_RX Pin Configuration!" +#endif +#ifndef RTE_UART2_RX_PIN_EN +#define RTE_UART2_RX_PIN_EN 1 +#endif + +// <h> DMA +// <e> Tx +// <o1> Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 +// </e> +#define RTE_UART2_DMA_TX_EN 1 +#define RTE_UART2_DMA_TX_CH 0 +// <e> Rx +// <o1> Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 +// </e> +#define RTE_UART2_DMA_RX_EN 1 +#define RTE_UART2_DMA_RX_CH 1 +// </h> DMA + +// </e> + +// <e> UART3 (Universal asynchronous receiver transmitter) +#define RTE_UART3 0 + +// <o> UART3_TX Pin <0=>Not used <1=>P0_0 <2=>P0_25 <3=>P4_28 +// <i> UART3 Serial Output pin +#define RTE_UART3_TX_ID 0 +#if (RTE_UART3_TX_ID == 0) +#define RTE_UART3_TX_PIN_EN 0 +#elif (RTE_UART3_TX_ID == 1) +#define RTE_UART3_TX_PORT 0 +#define RTE_UART3_TX_BIT 0 +#define RTE_UART3_TX_FUNC 2 +#elif (RTE_UART3_TX_ID == 2) +#define RTE_UART3_TX_PORT 0 +#define RTE_UART3_TX_BIT 25 +#define RTE_UART3_TX_FUNC 3 +#elif (RTE_UART3_TX_ID == 3) +#define RTE_UART3_TX_PORT 4 +#define RTE_UART3_TX_BIT 28 +#define RTE_UART3_TX_FUNC 3 +#else +#error "Invalid UART3_TX Pin Configuration!" +#endif +#ifndef RTE_UART3_TX_PIN_EN +#define RTE_UART3_TX_PIN_EN 1 +#endif + +// <o> UART3_RX Pin <0=>Not used <1=>P0_1 <2=>P0_26 <3=>P4_29 +// <i> UART3 Serial Input pin +#define RTE_UART3_RX_ID 0 +#if (RTE_UART3_RX_ID == 0) +#define RTE_UART3_RX_PIN_EN 0 +#elif (RTE_UART3_RX_ID == 1) +#define RTE_UART3_RX_PORT 0 +#define RTE_UART3_RX_BIT 1 +#define RTE_UART3_RX_FUNC 2 +#elif (RTE_UART3_RX_ID == 2) +#define RTE_UART3_RX_PORT 0 +#define RTE_UART3_RX_BIT 26 +#define RTE_UART3_RX_FUNC 3 +#elif (RTE_UART3_RX_ID == 3) +#define RTE_UART3_RX_PORT 4 +#define RTE_UART3_RX_BIT 29 +#define RTE_UART3_RX_FUNC 3 +#else +#error "Invalid UART3_RX Pin Configuration!" +#endif +#ifndef RTE_UART3_RX_PIN_EN +#define RTE_UART3_RX_PIN_EN 1 +#endif + +// <h> DMA +// <e> Tx +// <o1> Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 +// </e> +#define RTE_UART3_DMA_TX_EN 1 +#define RTE_UART3_DMA_TX_CH 0 +// <e> Rx +// <o1> Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 +// </e> +#define RTE_UART3_DMA_RX_EN 1 +#define RTE_UART3_DMA_RX_CH 1 +// </h> DMA + +// </e> + +// <e> CAN1 Controller [Driver_CAN1] +// <i> Configuration settings for Driver_CAN1 in component ::Drivers:CAN +#define RTE_CAN_CAN1 0 + +// <h> Pin Configuration +// <o> CAN1_RD <0=>Not used <1=>P0_0 <2=>P0_21 +// <i> CAN1 receiver input. +#define RTE_CAN1_RD_ID 0 +#if (RTE_CAN1_RD_ID == 0) + #define RTE_CAN1_RD_PIN_EN 0 +#elif (RTE_CAN1_RD_ID == 1) + #define RTE_CAN1_RD_PORT 0 + #define RTE_CAN1_RD_BIT 0 + #define RTE_CAN1_RD_FUNC 1 +#elif (RTE_CAN1_RD_ID == 2) + #define RTE_CAN1_RD_PORT 0 + #define RTE_CAN1_RD_BIT 21 + #define RTE_CAN1_RD_FUNC 3 +#else + #error "Invalid RTE_CAN1_RD Pin Configuration!" +#endif +#ifndef RTE_CAN1_RD_PIN_EN + #define RTE_CAN1_RD_PIN_EN 1 +#endif +// <o> CAN1_TD <0=>Not used <1=>P0_1 <2=>P0_22 +// <i> CAN1 transmitter output. +#define RTE_CAN1_TD_ID 0 +#if (RTE_CAN1_TD_ID == 0) + #define RTE_CAN1_TD_PIN_EN 0 +#elif (RTE_CAN1_TD_ID == 1) + #define RTE_CAN1_TD_PORT 0 + #define RTE_CAN1_TD_BIT 1 + #define RTE_CAN1_TD_FUNC 1 +#elif (RTE_CAN1_TD_ID == 2) + #define RTE_CAN1_TD_PORT 0 + #define RTE_CAN1_TD_BIT 22 + #define RTE_CAN1_TD_FUNC 3 +#else + #error "Invalid RTE_CAN1_TD Pin Configuration!" +#endif +#ifndef RTE_CAN1_TD_PIN_EN + #define RTE_CAN1_TD_PIN_EN 1 +#endif +// </h> Pin Configuration +// </e> CAN1 Controller [Driver_CAN1] + +// <e> CAN2 Controller [Driver_CAN2] +// <i> Configuration settings for Driver_CAN2 in component ::Drivers:CAN +#define RTE_CAN_CAN2 0 + +// <h> Pin Configuration +// <o> CAN2_RD <0=>Not used <1=>P0_4 <2=>P2_7 +// <i> CAN2 receiver input. +#define RTE_CAN2_RD_ID 0 +#if (RTE_CAN2_RD_ID == 0) + #define RTE_CAN2_RD_PIN_EN 0 +#elif (RTE_CAN2_RD_ID == 1) + #define RTE_CAN2_RD_PORT 0 + #define RTE_CAN2_RD_BIT 4 + #define RTE_CAN2_RD_FUNC 2 +#elif (RTE_CAN2_RD_ID == 2) + #define RTE_CAN2_RD_PORT 2 + #define RTE_CAN2_RD_BIT 7 + #define RTE_CAN2_RD_FUNC 1 +#else + #error "Invalid RTE_CAN2_RD Pin Configuration!" +#endif +#ifndef RTE_CAN2_RD_PIN_EN + #define RTE_CAN2_RD_PIN_EN 1 +#endif +// <o> CAN2_TD <0=>Not used <1=>P0_5 <2=>P2_8 +// <i> CAN2 transmitter output. +#define RTE_CAN2_TD_ID 0 +#if (RTE_CAN2_TD_ID == 0) + #define RTE_CAN2_TD_PIN_EN 0 +#elif (RTE_CAN2_TD_ID == 1) + #define RTE_CAN2_TD_PORT 0 + #define RTE_CAN2_TD_BIT 5 + #define RTE_CAN2_TD_FUNC 2 +#elif (RTE_CAN2_TD_ID == 2) + #define RTE_CAN2_TD_PORT 2 + #define RTE_CAN2_TD_BIT 8 + #define RTE_CAN2_TD_FUNC 1 +#else + #error "Invalid RTE_CAN2_TD Pin Configuration!" +#endif +#ifndef RTE_CAN2_TD_PIN_EN + #define RTE_CAN2_TD_PIN_EN 1 +#endif +// </h> Pin Configuration +// </e> CAN2 Controller [Driver_CAN2] + + +// <e> SSP0 (Synchronous Serial Port 0) [Driver_SPI0] +// <i> Configuration settings for Driver_SPI0 in component ::Drivers:SPI +#define RTE_SSP0 0 + +// <h> Pin Configuration +// <o> SSP0_SSEL <0=>Not used <1=>P0_16 <2=>P1_21 +// <i> Slave Select for SSP0 +#define RTE_SSP0_SSEL_PIN_SEL 1 +#if (RTE_SSP0_SSEL_PIN_SEL == 0) +#define RTE_SSP0_SSEL_PIN_EN 0 +#elif (RTE_SSP0_SSEL_PIN_SEL == 1) + #define RTE_SSP0_SSEL_PORT 0 + #define RTE_SSP0_SSEL_BIT 16 + #define RTE_SSP0_SSEL_FUNC 2 +#elif (RTE_SSP0_SSEL_PIN_SEL == 2) + #define RTE_SSP0_SSEL_PORT 1 + #define RTE_SSP0_SSEL_BIT 21 + #define RTE_SSP0_SSEL_FUNC 3 +#else + #error "Invalid SSP0 SSP0_SSEL Pin Configuration!" +#endif +#ifndef RTE_SSP0_SSEL_PIN_EN +#define RTE_SSP0_SSEL_PIN_EN 1 +#endif + +// <o> SSP0_SCK <0=>P0_15 <1=>P1_20 +// <i> Serial clock for SSP0 +#define RTE_SSP0_SCK_PIN_SEL 0 +#if (RTE_SSP0_SCK_PIN_SEL == 0) + #define RTE_SSP0_SCK_PORT 0 + #define RTE_SSP0_SCK_BIT 15 + #define RTE_SSP0_SCK_FUNC 2 +#elif (RTE_SSP0_SCK_PIN_SEL == 1) + #define RTE_SSP0_SCK_PORT 1 + #define RTE_SSP0_SCK_BIT 20 + #define RTE_SSP0_SCK_FUNC 3 +#else + #error "Invalid SSP0 SSP0_SCK Pin Configuration!" +#endif + +// <o> SSP0_MISO <0=>Not used <1=>P0_17 <2=>P1_23 +// <i> Master In Slave Out for SSP0 +#define RTE_SSP0_MISO_PIN_SEL 0 +#if (RTE_SSP0_MISO_PIN_SEL == 0) + #define RTE_SSP0_MISO_PIN_EN 0 +#elif (RTE_SSP0_MISO_PIN_SEL == 1) + #define RTE_SSP0_MISO_PORT 0 + #define RTE_SSP0_MISO_BIT 17 + #define RTE_SSP0_MISO_FUNC 2 +#elif (RTE_SSP0_MISO_PIN_SEL == 2) + #define RTE_SSP0_MISO_PORT 1 + #define RTE_SSP0_MISO_BIT 23 + #define RTE_SSP0_MISO_FUNC 3 +#else + #error "Invalid SSP0 SSP0_MISO Pin Configuration!" +#endif +#ifndef RTE_SSP0_MISO_PIN_EN +#define RTE_SSP0_MISO_PIN_EN 1 +#endif + +// <o> SSP0_MOSI <0=>Not used <1=>P0_18 <2=>P1_24 +// <i> Master Out Slave In for SSP0 +#define RTE_SSP0_MOSI_PIN_SEL 0 +#if (RTE_SSP0_MOSI_PIN_SEL == 0) + #define RTE_SSP0_MOSI_PIN_EN 0 +#elif (RTE_SSP0_MOSI_PIN_SEL == 1) + #define RTE_SSP0_MOSI_PORT 0 + #define RTE_SSP0_MOSI_BIT 18 + #define RTE_SSP0_MOSI_FUNC 2 +#elif (RTE_SSP0_MOSI_PIN_SEL == 2) + #define RTE_SSP0_MOSI_PORT 1 + #define RTE_SSP0_MOSI_BIT 24 + #define RTE_SSP0_MOSI_FUNC 3 +#else + #error "Invalid SSP0 SSP0_MOSI Pin Configuration!" +#endif +#ifndef RTE_SSP0_MOSI_PIN_EN +#define RTE_SSP0_MOSI_PIN_EN 1 +#endif + +// </h> +// <h> DMA +// <e> Tx +// <o1> Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 +// </e> +#define RTE_SSP0_DMA_TX_EN 0 +#define RTE_SSP0_DMA_TX_CH 0 +// <e> Rx +// <o1> Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 +// </e> +#define RTE_SSP0_DMA_RX_EN 0 +#define RTE_SSP0_DMA_RX_CH 1 +// </h> DMA +// </e> + +// <e> SSP1 (Synchronous Serial Port 1) [Driver_SPI1] +// <i> Configuration settings for Driver_SPI1 in component ::Drivers:SPI +#define RTE_SSP1 1 + +// <h> Pin Configuration +// <o> SSP1_SSEL <0=>Not used <1=>P0_6 +// <i> Slave Select for SSP1 +#define RTE_SSP1_SSEL_PIN_SEL 1 +#if (RTE_SSP1_SSEL_PIN_SEL == 0) + #define RTE_SSP1_SSEL_PIN_EN 0 +#elif (RTE_SSP1_SSEL_PIN_SEL == 1) + #define RTE_SSP1_SSEL_PORT 0 + #define RTE_SSP1_SSEL_BIT 6 + #define RTE_SSP1_SSEL_FUNC 2 +#else + #error "Invalid SSP1 SSP1_SSEL Pin Configuration!" +#endif +#ifndef RTE_SSP1_SSEL_PIN_EN +#define RTE_SSP1_SSEL_PIN_EN 1 +#endif + +// <o> SSP1_SCK <0=>P0_7 <1=>P1_31 +// <i> Serial clock for SSP1 +#define RTE_SSP1_SCK_PIN_SEL 0 +#if (RTE_SSP1_SCK_PIN_SEL == 0) + #define RTE_SSP1_SCK_PORT 0 + #define RTE_SSP1_SCK_BIT 7 + #define RTE_SSP1_SCK_FUNC 2 +#elif (RTE_SSP1_SCK_PIN_SEL == 1) + #define RTE_SSP1_SCK_PORT 1 + #define RTE_SSP1_SCK_BIT 31 + #define RTE_SSP1_SCK_FUNC 2 +#else + #error "Invalid SSP1 SSP1_SCK Pin Configuration!" +#endif + +// <o> SSP1_MISO <0=>Not used <1=>P0_8 +// <i> Master In Slave Out for SSP1 +#define RTE_SSP1_MISO_PIN_SEL 1 +#if (RTE_SSP1_MISO_PIN_SEL == 0) + #define RTE_SSP1_MISO_PIN_EN 0 +#elif (RTE_SSP1_MISO_PIN_SEL == 1) + #define RTE_SSP1_MISO_PORT 0 + #define RTE_SSP1_MISO_BIT 8 + #define RTE_SSP1_MISO_FUNC 2 +#else + #error "Invalid SSP1 SSP1_MISO Pin Configuration!" +#endif +#ifndef RTE_SSP1_MISO_PIN_EN +#define RTE_SSP1_MISO_PIN_EN 1 +#endif + +// <o> SSP1_MOSI <0=>Not used <1=>P0_9 +// <i> Master Out Slave In for SSP1 +#define RTE_SSP1_MOSI_PIN_SEL 1 +#if (RTE_SSP1_MOSI_PIN_SEL == 0) + #define RTE_SSP1_MOSI_PIN_EN 0 +#elif (RTE_SSP1_MOSI_PIN_SEL == 1) + #define RTE_SSP1_MOSI_PORT 0 + #define RTE_SSP1_MOSI_BIT 9 + #define RTE_SSP1_MOSI_FUNC 2 +#else + #error "Invalid SSP1 SSP1_MOSI Pin Configuration!" +#endif +#ifndef RTE_SSP1_MOSI_PIN_EN +#define RTE_SSP1_MOSI_PIN_EN 1 +#endif + +// </h> +// <h> DMA +// <e> Tx +// <o1> Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 +// </e> +#define RTE_SSP1_DMA_TX_EN 0 +#define RTE_SSP1_DMA_TX_CH 2 +// <e> Rx +// <o1> Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 +// </e> +#define RTE_SSP1_DMA_RX_EN 0 +#define RTE_SSP1_DMA_RX_CH 3 +// </h> DMA +// </e> + + +// <e> SPI (Serial Peripheral Interface) [Driver_SPI2] +// <i> Configuration settings for Driver_SPI2 in component ::Drivers:SPI +#define RTE_SPI 0 + +// <h> Pin Configuration +// <o> SPI_SSEL <0=>Not used <1=>P0_16 +// <i> Slave Select for SPI +#define RTE_SPI_SSEL_PIN_SEL 0 +#if (RTE_SPI_SSEL_PIN_SEL == 0) +#define RTE_SPI_SSEL_PIN_EN 0 +#elif (RTE_SPI_SSEL_PIN_SEL == 1) + #define RTE_SPI_SSEL_PORT 0 + #define RTE_SPI_SSEL_BIT 16 + #define RTE_SPI_SSEL_FUNC 3 +#else + #error "Invalid SPI SPI_SSEL Pin Configuration!" +#endif +#ifndef RTE_SPI_SSEL_PIN_EN +#define RTE_SPI_SSEL_PIN_EN 1 +#endif +// <o> SPI_SCK <0=>P0_15 +// <i> Serial clock for SPI +#define RTE_SPI_SCK_PIN_SEL 0 +#if (RTE_SPI_SCK_PIN_SEL == 0) + #define RTE_SPI_SCK_PORT 0 + #define RTE_SPI_SCK_BIT 15 + #define RTE_SPI_SCK_FUNC 3 +#else + #error "Invalid SPI SPI_SCK Pin Configuration!" +#endif +// <o> SPI_MISO <0=>Not used <1=>P0_17 +// <i> Master In Slave Out for SPI +#define RTE_SPI_MISO_PIN_SEL 0 +#if (RTE_SPI_MISO_PIN_SEL == 0) + #define RTE_SPI_MISO_PIN_EN 0 +#elif (RTE_SPI_MISO_PIN_SEL == 1) + #define RTE_SPI_MISO_PORT 0 + #define RTE_SPI_MISO_BIT 17 + #define RTE_SPI_MISO_FUNC 3 +#else + #error "Invalid SPI SPI_MISO Pin Configuration!" +#endif +#ifndef RTE_SPI_MISO_PIN_EN +#define RTE_SPI_MISO_PIN_EN 1 +#endif + +// <o> SPI_MOSI <0=>Not used <1=>P0_18 +// <i> Master Out Slave In for SPI +#define RTE_SPI_MOSI_PIN_SEL 0 +#if (RTE_SPI_MOSI_PIN_SEL == 0) + #define RTE_SPI_MOSI_PIN_EN 0 +#elif (RTE_SPI_MOSI_PIN_SEL == 1) + #define RTE_SPI_MOSI_PORT 0 + #define RTE_SPI_MOSI_BIT 18 + #define RTE_SPI_MOSI_FUNC 3 +#else + #error "Invalid SPI SPI_MOSI Pin Configuration!" +#endif +#ifndef RTE_SPI_MOSI_PIN_EN +#define RTE_SPI_MOSI_PIN_EN 1 +#endif + +// </h> Pin Configuration +// </e> SPI (Serial Peripheral Interface) [Driver_SPI2] + + +// <e> I2S0 (Integrated Interchip Sound 0) [Driver_SAI0] +// <i> Configuration settings for Driver_SAI0 in component ::Drivers:SAI +#define RTE_I2S0 0 + +// <h> Pin Configuration +// <o> I2S0_RX_SCK <0=>Not used <1=>P0_4 <2=>P0_23 +// <i> Receive clock for I2S0 +#define RTE_I2S0_RX_SCK_PIN_SEL 1 +#if (RTE_I2S0_RX_SCK_PIN_SEL == 0) +#define RTE_I2S0_RX_SCK_PIN_EN 0 +#elif (RTE_I2S0_RX_SCK_PIN_SEL == 1) + #define RTE_I2S0_RX_SCK_PORT 0 + #define RTE_I2S0_RX_SCK_BIT 4 + #define RTE_I2S0_RX_SCK_FUNC 1 +#elif (RTE_I2S0_RX_SCK_PIN_SEL == 2) + #define RTE_I2S0_RX_SCK_PORT 0 + #define RTE_I2S0_RX_SCK_BIT 23 + #define RTE_I2S0_RX_SCK_FUNC 2 +#else + #error "Invalid I2S0 I2S0_RX_SCK Pin Configuration!" +#endif +#ifndef RTE_I2S0_RX_SCK_PIN_EN +#define RTE_I2S0_RX_SCK_PIN_EN 1 +#endif +// <o> I2S0_RX_WS <0=>Not used <1=>P0_5 <2=>P0_24 +// <i> Receive word select for I2S0 +#define RTE_I2S0_RX_WS_PIN_SEL 1 +#if (RTE_I2S0_RX_WS_PIN_SEL == 0) +#define RTE_I2S0_RX_WS_PIN_EN 0 +#elif (RTE_I2S0_RX_WS_PIN_SEL == 1) + #define RTE_I2S0_RX_WS_PORT 0 + #define RTE_I2S0_RX_WS_BIT 5 + #define RTE_I2S0_RX_WS_FUNC 1 +#elif (RTE_I2S0_RX_WS_PIN_SEL == 2) + #define RTE_I2S0_RX_WS_PORT 0 + #define RTE_I2S0_RX_WS_BIT 24 + #define RTE_I2S0_RX_WS_FUNC 2 +#else + #error "Invalid I2S0 I2S0_RX_WS Pin Configuration!" +#endif +#ifndef RTE_I2S0_RX_WS_PIN_EN +#define RTE_I2S0_RX_WS_PIN_EN 1 +#endif +// <o> I2S0_RX_SDA <0=>Not used <1=>P0_6 <2=>P0_25 +// <i> Receive master clock for I2S0 +#define RTE_I2S0_RX_SDA_PIN_SEL 1 +#if (RTE_I2S0_RX_SDA_PIN_SEL == 0) +#define RTE_I2S0_RX_SDA_PIN_EN 0 +#elif (RTE_I2S0_RX_SDA_PIN_SEL == 1) + #define RTE_I2S0_RX_SDA_PORT 0 + #define RTE_I2S0_RX_SDA_BIT 6 + #define RTE_I2S0_RX_SDA_FUNC 1 +#elif (RTE_I2S0_RX_SDA_PIN_SEL == 2) + #define RTE_I2S0_RX_SDA_PORT 0 + #define RTE_I2S0_RX_SDA_BIT 25 + #define RTE_I2S0_RX_SDA_FUNC 2 +#else + #error "Invalid I2S0 I2S0_RX_SDA Pin Configuration!" +#endif +#ifndef RTE_I2S0_RX_SDA_PIN_EN +#define RTE_I2S0_RX_SDA_PIN_EN 1 +#endif +// <o> I2S0_RX_MCLK <0=>Not used <1=>P4_28 +// <i> Receive master clock for I2S0 +#define RTE_I2S0_RX_MCLK_PIN_SEL 0 +#if (RTE_I2S0_RX_MCLK_PIN_SEL == 0) +#define RTE_I2S0_RX_MCLK_PIN_EN 0 +#elif (RTE_I2S0_RX_MCLK_PIN_SEL == 1) + #define RTE_I2S0_RX_MCLK_PORT 4 + #define RTE_I2S0_RX_MCLK_BIT 28 + #define RTE_I2S0_RX_MCLK_FUNC 1 +#else + #error "Invalid I2S0 I2S0_RX_MCLK Pin Configuration!" +#endif +#ifndef RTE_I2S0_RX_MCLK_PIN_EN +#define RTE_I2S0_RX_MCLK_PIN_EN 1 +#endif +// <o> I2S0_TX_SCK <0=>Not used <1=>P0_7 <2=>P2_11 +// <i> Transmit clock for I2S0 +#define RTE_I2S0_TX_SCK_PIN_SEL 1 +#if (RTE_I2S0_TX_SCK_PIN_SEL == 0) +#define RTE_I2S0_TX_SCK_PIN_EN 0 +#elif (RTE_I2S0_TX_SCK_PIN_SEL == 1) + #define RTE_I2S0_TX_SCK_PORT 0 + #define RTE_I2S0_TX_SCK_BIT 7 + #define RTE_I2S0_TX_SCK_FUNC 1 +#elif (RTE_I2S0_TX_SCK_PIN_SEL == 2) + #define RTE_I2S0_TX_SCK_PORT 2 + #define RTE_I2S0_TX_SCK_BIT 11 + #define RTE_I2S0_TX_SCK_FUNC 3 +#else + #error "Invalid I2S0 I2S0_TX_SCK Pin Configuration!" +#endif +#ifndef RTE_I2S0_TX_SCK_PIN_EN +#define RTE_I2S0_TX_SCK_PIN_EN 1 +#endif +// <o> I2S0_TX_WS <0=>Not used <1=>P0_8 <2=>P2_12 +// <i> Transmit word select for I2S0 +#define RTE_I2S0_TX_WS_PIN_SEL 1 +#if (RTE_I2S0_TX_WS_PIN_SEL == 0) +#define RTE_I2S0_TX_WS_PIN_EN 0 +#elif (RTE_I2S0_TX_WS_PIN_SEL == 1) + #define RTE_I2S0_TX_WS_PORT 0 + #define RTE_I2S0_TX_WS_BIT 8 + #define RTE_I2S0_TX_WS_FUNC 1 +#elif (RTE_I2S0_TX_WS_PIN_SEL == 2) + #define RTE_I2S0_TX_WS_PORT 2 + #define RTE_I2S0_TX_WS_BIT 12 + #define RTE_I2S0_TX_WS_FUNC 3 +#else + #error "Invalid I2S0 I2S0_TX_WS Pin Configuration!" +#endif +#ifndef RTE_I2S0_TX_WS_PIN_EN +#define RTE_I2S0_TX_WS_PIN_EN 1 +#endif +// <o> I2S0_TX_SDA <0=>Not used <1=>P0_9 <2=>P2_13 +// <i> Transmit data for I2S0 +#define RTE_I2S0_TX_SDA_PIN_SEL 1 +#if (RTE_I2S0_TX_SDA_PIN_SEL == 0) +#define RTE_I2S0_TX_SDA_PIN_EN 0 +#elif (RTE_I2S0_TX_SDA_PIN_SEL == 1) + #define RTE_I2S0_TX_SDA_PORT 0 + #define RTE_I2S0_TX_SDA_BIT 9 + #define RTE_I2S0_TX_SDA_FUNC 1 +#elif (RTE_I2S0_TX_SDA_PIN_SEL == 2) + #define RTE_I2S0_TX_SDA_PORT 2 + #define RTE_I2S0_TX_SDA_BIT 13 + #define RTE_I2S0_TX_SDA_FUNC 3 +#else + #error "Invalid I2S0 I2S0_TX_SDA Pin Configuration!" +#endif +#ifndef RTE_I2S0_TX_SDA_PIN_EN +#define RTE_I2S0_TX_SDA_PIN_EN 1 +#endif +// <o> I2S0_TX_MCLK <0=>Not used <1=>P4_29 +// <i> Transmit master clock for I2S0 +#define RTE_I2S0_TX_MCLK_PIN_SEL 1 +#if (RTE_I2S0_TX_MCLK_PIN_SEL == 0) +#define RTE_I2S0_TX_MCLK_PIN_EN 0 +#elif (RTE_I2S0_TX_MCLK_PIN_SEL == 1) + #define RTE_I2S0_TX_MCLK_PORT 4 + #define RTE_I2S0_TX_MCLK_BIT 29 + #define RTE_I2S0_TX_MCLK_FUNC 1 +#else + #error "Invalid I2S0 I2S0_TX_MCLK Pin Configuration!" +#endif +#ifndef RTE_I2S0_TX_MCLK_PIN_EN +#define RTE_I2S0_TX_MCLK_PIN_EN 1 +#endif +// </h> Pin Configuration + +// <h> DMA +// <e> Tx +// <o1> Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 +// <o2> Peripheral <0=>9 (DMAMUXPER9) +// </e> +#define RTE_I2S0_DMA_TX_EN 1 +#define RTE_I2S0_DMA_TX_CH 0 +// <e> Rx +// <o1> Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 +// <o2> Peripheral <0=>10 (DMAMUXPER10) +// </e> +#define RTE_I2S0_DMA_RX_EN 1 +#define RTE_I2S0_DMA_RX_CH 1 +// </h> DMA +// </e> I2S0 (Integrated Interchip Sound 0) [Driver_SAI0] + +#endif /* __RTE_DEVICE_H */ diff --git a/F2024/coe718/labs/lab1/Boards/Keil/MCB1700/Blinky_ULp/RTE/Device/LPC1768/startup_LPC17xx.s b/F2024/coe718/labs/lab1/Boards/Keil/MCB1700/Blinky_ULp/RTE/Device/LPC1768/startup_LPC17xx.s new file mode 100755 index 0000000..02a0f9a --- /dev/null +++ b/F2024/coe718/labs/lab1/Boards/Keil/MCB1700/Blinky_ULp/RTE/Device/LPC1768/startup_LPC17xx.s @@ -0,0 +1,287 @@ +;/**************************************************************************//** +; * @file startup_LPC17xx.s +; * @brief CMSIS Cortex-M3 Core Device Startup File for +; * NXP LPC17xx Device Series +; * @version V1.10 +; * @date 06. April 2011 +; * +; * @note +; * Copyright (C) 2009-2011 ARM Limited. All rights reserved. +; * +; * @par +; * ARM Limited (ARM) is supplying this software for use with Cortex-M +; * processor based microcontrollers. This file can be freely distributed +; * within development tools that are supporting such ARM based processors. +; * +; * @par +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; * +; ******************************************************************************/ + +; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ + +; <h> Stack Configuration +; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Stack_Size EQU 0x00000200 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; <h> Heap Configuration +; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Heap_Size EQU 0x00000000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WDT_IRQHandler ; 16: Watchdog Timer + DCD TIMER0_IRQHandler ; 17: Timer0 + DCD TIMER1_IRQHandler ; 18: Timer1 + DCD TIMER2_IRQHandler ; 19: Timer2 + DCD TIMER3_IRQHandler ; 20: Timer3 + DCD UART0_IRQHandler ; 21: UART0 + DCD UART1_IRQHandler ; 22: UART1 + DCD UART2_IRQHandler ; 23: UART2 + DCD UART3_IRQHandler ; 24: UART3 + DCD PWM1_IRQHandler ; 25: PWM1 + DCD I2C0_IRQHandler ; 26: I2C0 + DCD I2C1_IRQHandler ; 27: I2C1 + DCD I2C2_IRQHandler ; 28: I2C2 + DCD SPI_IRQHandler ; 29: SPI + DCD SSP0_IRQHandler ; 30: SSP0 + DCD SSP1_IRQHandler ; 31: SSP1 + DCD PLL0_IRQHandler ; 32: PLL0 Lock (Main PLL) + DCD RTC_IRQHandler ; 33: Real Time Clock + DCD EINT0_IRQHandler ; 34: External Interrupt 0 + DCD EINT1_IRQHandler ; 35: External Interrupt 1 + DCD EINT2_IRQHandler ; 36: External Interrupt 2 + DCD EINT3_IRQHandler ; 37: External Interrupt 3 + DCD ADC_IRQHandler ; 38: A/D Converter + DCD BOD_IRQHandler ; 39: Brown-Out Detect + DCD USB_IRQHandler ; 40: USB + DCD CAN_IRQHandler ; 41: CAN + DCD DMA_IRQHandler ; 42: General Purpose DMA + DCD I2S_IRQHandler ; 43: I2S + DCD ENET_IRQHandler ; 44: Ethernet + DCD RIT_IRQHandler ; 45: Repetitive Interrupt Timer + DCD MCPWM_IRQHandler ; 46: Motor Control PWM + DCD QEI_IRQHandler ; 47: Quadrature Encoder Interface + DCD PLL1_IRQHandler ; 48: PLL1 Lock (USB PLL) + DCD USBActivity_IRQHandler ; 49: USB Activity interrupt to wakeup + DCD CANActivity_IRQHandler ; 50: CAN Activity interrupt to wakeup + + + IF :LNOT::DEF:NO_CRP + AREA |.ARM.__at_0x02FC|, CODE, READONLY +CRP_Key DCD 0xFFFFFFFF + ENDIF + + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WDT_IRQHandler [WEAK] + EXPORT TIMER0_IRQHandler [WEAK] + EXPORT TIMER1_IRQHandler [WEAK] + EXPORT TIMER2_IRQHandler [WEAK] + EXPORT TIMER3_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT I2C2_IRQHandler [WEAK] + EXPORT SPI_IRQHandler [WEAK] + EXPORT SSP0_IRQHandler [WEAK] + EXPORT SSP1_IRQHandler [WEAK] + EXPORT PLL0_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT EINT0_IRQHandler [WEAK] + EXPORT EINT1_IRQHandler [WEAK] + EXPORT EINT2_IRQHandler [WEAK] + EXPORT EINT3_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT BOD_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + EXPORT CAN_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT I2S_IRQHandler [WEAK] + EXPORT ENET_IRQHandler [WEAK] + EXPORT RIT_IRQHandler [WEAK] + EXPORT MCPWM_IRQHandler [WEAK] + EXPORT QEI_IRQHandler [WEAK] + EXPORT PLL1_IRQHandler [WEAK] + EXPORT USBActivity_IRQHandler [WEAK] + EXPORT CANActivity_IRQHandler [WEAK] + +WDT_IRQHandler +TIMER0_IRQHandler +TIMER1_IRQHandler +TIMER2_IRQHandler +TIMER3_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +PWM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +I2C2_IRQHandler +SPI_IRQHandler +SSP0_IRQHandler +SSP1_IRQHandler +PLL0_IRQHandler +RTC_IRQHandler +EINT0_IRQHandler +EINT1_IRQHandler +EINT2_IRQHandler +EINT3_IRQHandler +ADC_IRQHandler +BOD_IRQHandler +USB_IRQHandler +CAN_IRQHandler +DMA_IRQHandler +I2S_IRQHandler +ENET_IRQHandler +RIT_IRQHandler +MCPWM_IRQHandler +QEI_IRQHandler +PLL1_IRQHandler +USBActivity_IRQHandler +CANActivity_IRQHandler + + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + + END diff --git a/F2024/coe718/labs/lab1/Boards/Keil/MCB1700/Blinky_ULp/RTE/Device/LPC1768/system_LPC17xx.c b/F2024/coe718/labs/lab1/Boards/Keil/MCB1700/Blinky_ULp/RTE/Device/LPC1768/system_LPC17xx.c new file mode 100755 index 0000000..e243824 --- /dev/null +++ b/F2024/coe718/labs/lab1/Boards/Keil/MCB1700/Blinky_ULp/RTE/Device/LPC1768/system_LPC17xx.c @@ -0,0 +1,574 @@ +/**************************************************************************//** + * @file system_LPC17xx.c + * @brief CMSIS Cortex-M3 Device System Source File for + * NXP LPC17xx Device Series + * @version V1.13 + * @date 18. April 2012 + * + * @note + * Copyright (C) 2009-2012 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + + +#include <stdint.h> +#include "LPC17xx.h" + + +/** @addtogroup LPC17xx_System + * @{ + */ + +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +*/ + +/*--------------------- Clock Configuration ---------------------------------- +// +// <e> Clock Configuration +// <h> System Controls and Status Register (SCS) +// <o1.4> OSCRANGE: Main Oscillator Range Select +// <0=> 1 MHz to 20 MHz +// <1=> 15 MHz to 25 MHz +// <e1.5> OSCEN: Main Oscillator Enable +// </e> +// </h> +// +// <h> Clock Source Select Register (CLKSRCSEL) +// <o2.0..1> CLKSRC: PLL Clock Source Selection +// <0=> Internal RC oscillator +// <1=> Main oscillator +// <2=> RTC oscillator +// </h> +// +// <e3> PLL0 Configuration (Main PLL) +// <h> PLL0 Configuration Register (PLL0CFG) +// <i> F_cco0 = (2 * M * F_in) / N +// <i> F_in must be in the range of 32 kHz to 50 MHz +// <i> F_cco0 must be in the range of 275 MHz to 550 MHz +// <o4.0..14> MSEL: PLL Multiplier Selection +// <6-32768><#-1> +// <i> M Value +// <o4.16..23> NSEL: PLL Divider Selection +// <1-256><#-1> +// <i> N Value +// </h> +// </e> +// +// <e5> PLL1 Configuration (USB PLL) +// <h> PLL1 Configuration Register (PLL1CFG) +// <i> F_usb = M * F_osc or F_usb = F_cco1 / (2 * P) +// <i> F_cco1 = F_osc * M * 2 * P +// <i> F_cco1 must be in the range of 156 MHz to 320 MHz +// <o6.0..4> MSEL: PLL Multiplier Selection +// <1-32><#-1> +// <i> M Value (for USB maximum value is 4) +// <o6.5..6> PSEL: PLL Divider Selection +// <0=> 1 +// <1=> 2 +// <2=> 4 +// <3=> 8 +// <i> P Value +// </h> +// </e> +// +// <h> CPU Clock Configuration Register (CCLKCFG) +// <o7.0..7> CCLKSEL: Divide Value for CPU Clock from PLL0 +// <1-256><#-1> +// </h> +// +// <h> USB Clock Configuration Register (USBCLKCFG) +// <o8.0..3> USBSEL: Divide Value for USB Clock from PLL0 +// <0-15> +// <i> Divide is USBSEL + 1 +// </h> +// +// <h> Peripheral Clock Selection Register 0 (PCLKSEL0) +// <o9.0..1> PCLK_WDT: Peripheral Clock Selection for WDT +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Cclk / 8 +// <o9.2..3> PCLK_TIMER0: Peripheral Clock Selection for TIMER0 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Cclk / 8 +// <o9.4..5> PCLK_TIMER1: Peripheral Clock Selection for TIMER1 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Cclk / 8 +// <o9.6..7> PCLK_UART0: Peripheral Clock Selection for UART0 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Cclk / 8 +// <o9.8..9> PCLK_UART1: Peripheral Clock Selection for UART1 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Cclk / 8 +// <o9.12..13> PCLK_PWM1: Peripheral Clock Selection for PWM1 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Cclk / 8 +// <o9.14..15> PCLK_I2C0: Peripheral Clock Selection for I2C0 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Cclk / 8 +// <o9.16..17> PCLK_SPI: Peripheral Clock Selection for SPI +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Cclk / 8 +// <o9.20..21> PCLK_SSP1: Peripheral Clock Selection for SSP1 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Cclk / 8 +// <o9.22..23> PCLK_DAC: Peripheral Clock Selection for DAC +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Cclk / 8 +// <o9.24..25> PCLK_ADC: Peripheral Clock Selection for ADC +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Cclk / 8 +// <o9.26..27> PCLK_CAN1: Peripheral Clock Selection for CAN1 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Cclk / 6 +// <o9.28..29> PCLK_CAN2: Peripheral Clock Selection for CAN2 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Cclk / 6 +// <o9.30..31> PCLK_ACF: Peripheral Clock Selection for ACF +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Cclk / 6 +// </h> +// +// <h> Peripheral Clock Selection Register 1 (PCLKSEL1) +// <o10.0..1> PCLK_QEI: Peripheral Clock Selection for the Quadrature Encoder Interface +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Cclk / 8 +// <o10.2..3> PCLK_GPIO: Peripheral Clock Selection for GPIOs +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Cclk / 8 +// <o10.4..5> PCLK_PCB: Peripheral Clock Selection for the Pin Connect Block +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Cclk / 8 +// <o10.6..7> PCLK_I2C1: Peripheral Clock Selection for I2C1 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Cclk / 8 +// <o10.10..11> PCLK_SSP0: Peripheral Clock Selection for SSP0 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Cclk / 8 +// <o10.12..13> PCLK_TIMER2: Peripheral Clock Selection for TIMER2 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Cclk / 8 +// <o10.14..15> PCLK_TIMER3: Peripheral Clock Selection for TIMER3 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Cclk / 8 +// <o10.16..17> PCLK_UART2: Peripheral Clock Selection for UART2 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Cclk / 8 +// <o10.18..19> PCLK_UART3: Peripheral Clock Selection for UART3 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Cclk / 8 +// <o10.20..21> PCLK_I2C2: Peripheral Clock Selection for I2C2 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Cclk / 8 +// <o10.22..23> PCLK_I2S: Peripheral Clock Selection for I2S +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Cclk / 8 +// <o10.26..27> PCLK_RIT: Peripheral Clock Selection for the Repetitive Interrupt Timer +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Cclk / 8 +// <o10.28..29> PCLK_SYSCON: Peripheral Clock Selection for the System Control Block +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Cclk / 8 +// <o10.30..31> PCLK_MC: Peripheral Clock Selection for the Motor Control PWM +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Cclk / 8 +// </h> +// +// <h> Power Control for Peripherals Register (PCONP) +// <o11.1> PCTIM0: Timer/Counter 0 power/clock enable +// <o11.2> PCTIM1: Timer/Counter 1 power/clock enable +// <o11.3> PCUART0: UART 0 power/clock enable +// <o11.4> PCUART1: UART 1 power/clock enable +// <o11.6> PCPWM1: PWM 1 power/clock enable +// <o11.7> PCI2C0: I2C interface 0 power/clock enable +// <o11.8> PCSPI: SPI interface power/clock enable +// <o11.9> PCRTC: RTC power/clock enable +// <o11.10> PCSSP1: SSP interface 1 power/clock enable +// <o11.12> PCAD: A/D converter power/clock enable +// <o11.13> PCCAN1: CAN controller 1 power/clock enable +// <o11.14> PCCAN2: CAN controller 2 power/clock enable +// <o11.15> PCGPIO: GPIOs power/clock enable +// <o11.16> PCRIT: Repetitive interrupt timer power/clock enable +// <o11.17> PCMC: Motor control PWM power/clock enable +// <o11.18> PCQEI: Quadrature encoder interface power/clock enable +// <o11.19> PCI2C1: I2C interface 1 power/clock enable +// <o11.21> PCSSP0: SSP interface 0 power/clock enable +// <o11.22> PCTIM2: Timer 2 power/clock enable +// <o11.23> PCTIM3: Timer 3 power/clock enable +// <o11.24> PCUART2: UART 2 power/clock enable +// <o11.25> PCUART3: UART 3 power/clock enable +// <o11.26> PCI2C2: I2C interface 2 power/clock enable +// <o11.27> PCI2S: I2S interface power/clock enable +// <o11.29> PCGPDMA: GP DMA function power/clock enable +// <o11.30> PCENET: Ethernet block power/clock enable +// <o11.31> PCUSB: USB interface power/clock enable +// </h> +// +// <h> Clock Output Configuration Register (CLKOUTCFG) +// <o12.0..3> CLKOUTSEL: Selects clock source for CLKOUT +// <0=> CPU clock +// <1=> Main oscillator +// <2=> Internal RC oscillator +// <3=> USB clock +// <4=> RTC oscillator +// <o12.4..7> CLKOUTDIV: Selects clock divider for CLKOUT +// <1-16><#-1> +// <o12.8> CLKOUT_EN: CLKOUT enable control +// </h> +// +// </e> +*/ + + + +/** @addtogroup LPC17xx_System_Defines LPC17xx System Defines + @{ + */ + +#define CLOCK_SETUP 1 +#define SCS_Val 0x00000020 +#define CLKSRCSEL_Val 0x00000001 +#define PLL0_SETUP 1 +#define PLL0CFG_Val 0x00050063 +#define PLL1_SETUP 1 +#define PLL1CFG_Val 0x00000023 +#define CCLKCFG_Val 0x00000003 +#define USBCLKCFG_Val 0x00000000 +#define PCLKSEL0_Val 0x00000000 +#define PCLKSEL1_Val 0x00000000 +#define PCONP_Val 0x042887DE +#define CLKOUTCFG_Val 0x00000000 + + +/*--------------------- Flash Accelerator Configuration ---------------------- +// +// <e> Flash Accelerator Configuration +// <o1.12..15> FLASHTIM: Flash Access Time +// <0=> 1 CPU clock (for CPU clock up to 20 MHz) +// <1=> 2 CPU clocks (for CPU clock up to 40 MHz) +// <2=> 3 CPU clocks (for CPU clock up to 60 MHz) +// <3=> 4 CPU clocks (for CPU clock up to 80 MHz) +// <4=> 5 CPU clocks (for CPU clock up to 100 MHz) +// <5=> 6 CPU clocks (for any CPU clock) +// </e> +*/ +#define FLASH_SETUP 1 +#define FLASHCFG_Val 0x00004000 + +/* +//-------- <<< end of configuration section >>> ------------------------------ +*/ + +/*---------------------------------------------------------------------------- + Check the register settings + *----------------------------------------------------------------------------*/ +#define CHECK_RANGE(val, min, max) ((val < min) || (val > max)) +#define CHECK_RSVD(val, mask) (val & mask) + +/* Clock Configuration -------------------------------------------------------*/ +#if (CHECK_RSVD((SCS_Val), ~0x00000030)) + #error "SCS: Invalid values of reserved bits!" +#endif + +#if (CHECK_RANGE((CLKSRCSEL_Val), 0, 2)) + #error "CLKSRCSEL: Value out of range!" +#endif + +#if (CHECK_RSVD((PLL0CFG_Val), ~0x00FF7FFF)) + #error "PLL0CFG: Invalid values of reserved bits!" +#endif + +#if (CHECK_RSVD((PLL1CFG_Val), ~0x0000007F)) + #error "PLL1CFG: Invalid values of reserved bits!" +#endif + +#if (PLL0_SETUP) /* if PLL0 is used */ + #if (CCLKCFG_Val < 2) /* CCLKSEL must be greater then 1 */ + #error "CCLKCFG: CCLKSEL must be greater then 1 if PLL0 is used!" + #endif +#endif + +#if (CHECK_RANGE((CCLKCFG_Val), 0, 255)) + #error "CCLKCFG: Value out of range!" +#endif + +#if (CHECK_RSVD((USBCLKCFG_Val), ~0x0000000F)) + #error "USBCLKCFG: Invalid values of reserved bits!" +#endif + +#if (CHECK_RSVD((PCLKSEL0_Val), 0x000C0C00)) + #error "PCLKSEL0: Invalid values of reserved bits!" +#endif + +#if (CHECK_RSVD((PCLKSEL1_Val), 0x03000300)) + #error "PCLKSEL1: Invalid values of reserved bits!" +#endif + +#if (CHECK_RSVD((PCONP_Val), 0x10100821)) + #error "PCONP: Invalid values of reserved bits!" +#endif + +#if (CHECK_RSVD((CLKOUTCFG_Val), ~0x000001FF)) + #error "CLKOUTCFG: Invalid values of reserved bits!" +#endif + +/* Flash Accelerator Configuration -------------------------------------------*/ +#if (CHECK_RSVD((FLASHCFG_Val), ~0x0000F000)) + #error "FLASHCFG: Invalid values of reserved bits!" +#endif + + +/*---------------------------------------------------------------------------- + DEFINES + *----------------------------------------------------------------------------*/ + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (12000000UL) /* Oscillator frequency */ +#define OSC_CLK ( XTAL) /* Main oscillator frequency */ +#define RTC_CLK ( 32768UL) /* RTC oscillator frequency */ +#define IRC_OSC ( 4000000UL) /* Internal RC oscillator frequency */ + + +/* F_cco0 = (2 * M * F_in) / N */ +#define __M (((PLL0CFG_Val ) & 0x7FFF) + 1) +#define __N (((PLL0CFG_Val >> 16) & 0x00FF) + 1) +#define __FCCO(__F_IN) ((2ULL * __M * __F_IN) / __N) +#define __CCLK_DIV (((CCLKCFG_Val ) & 0x00FF) + 1) + +/* Determine core clock frequency according to settings */ + #if (PLL0_SETUP) + #if ((CLKSRCSEL_Val & 0x03) == 1) + #define __CORE_CLK (__FCCO(OSC_CLK) / __CCLK_DIV) + #elif ((CLKSRCSEL_Val & 0x03) == 2) + #define __CORE_CLK (__FCCO(RTC_CLK) / __CCLK_DIV) + #else + #define __CORE_CLK (__FCCO(IRC_OSC) / __CCLK_DIV) + #endif + #else + #if ((CLKSRCSEL_Val & 0x03) == 1) + #define __CORE_CLK (OSC_CLK / __CCLK_DIV) + #elif ((CLKSRCSEL_Val & 0x03) == 2) + #define __CORE_CLK (RTC_CLK / __CCLK_DIV) + #else + #define __CORE_CLK (IRC_OSC / __CCLK_DIV) + #endif + #endif + +/** + * @} + */ + + +/** @addtogroup LPC17xx_System_Public_Variables LPC17xx System Public Variables + @{ + */ +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = __CORE_CLK;/*!< System Clock Frequency (Core Clock)*/ + +/** + * @} + */ + + +/** @addtogroup LPC17xx_System_Public_Functions LPC17xx System Public Functions + @{ + */ + +/** + * Update SystemCoreClock variable + * + * @param none + * @return none + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ +{ + /* Determine clock frequency according to clock register values */ + if (((LPC_SC->PLL0STAT >> 24) & 3) == 3) { /* If PLL0 enabled and connected */ + switch (LPC_SC->CLKSRCSEL & 0x03) { + case 0: /* Int. RC oscillator => PLL0 */ + case 3: /* Reserved, default to Int. RC */ + SystemCoreClock = (IRC_OSC * + ((2ULL * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) / + (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) / + ((LPC_SC->CCLKCFG & 0xFF)+ 1)); + break; + case 1: /* Main oscillator => PLL0 */ + SystemCoreClock = (OSC_CLK * + ((2ULL * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) / + (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) / + ((LPC_SC->CCLKCFG & 0xFF)+ 1)); + break; + case 2: /* RTC oscillator => PLL0 */ + SystemCoreClock = (RTC_CLK * + ((2ULL * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) / + (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) / + ((LPC_SC->CCLKCFG & 0xFF)+ 1)); + break; + } + } else { + switch (LPC_SC->CLKSRCSEL & 0x03) { + case 0: /* Int. RC oscillator => PLL0 */ + case 3: /* Reserved, default to Int. RC */ + SystemCoreClock = IRC_OSC / ((LPC_SC->CCLKCFG & 0xFF)+ 1); + break; + case 1: /* Main oscillator => PLL0 */ + SystemCoreClock = OSC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1); + break; + case 2: /* RTC oscillator => PLL0 */ + SystemCoreClock = RTC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1); + break; + } + } + +} + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System. + */ +void SystemInit (void) +{ +#if (CLOCK_SETUP) /* Clock Setup */ + LPC_SC->SCS = SCS_Val; + if (LPC_SC->SCS & (1 << 5)) { /* If Main Oscillator is enabled */ + while ((LPC_SC->SCS & (1<<6)) == 0);/* Wait for Oscillator to be ready */ + } + + LPC_SC->CCLKCFG = CCLKCFG_Val; /* Setup Clock Divider */ + /* Periphral clock must be selected before PLL0 enabling and connecting + * - according errata.lpc1768-16.March.2010 - + */ + LPC_SC->PCLKSEL0 = PCLKSEL0_Val; /* Peripheral Clock Selection */ + LPC_SC->PCLKSEL1 = PCLKSEL1_Val; + + LPC_SC->CLKSRCSEL = CLKSRCSEL_Val; /* Select Clock Source sysclk / PLL0 */ + +#if (PLL0_SETUP) + LPC_SC->PLL0CFG = PLL0CFG_Val; /* configure PLL0 */ + LPC_SC->PLL0FEED = 0xAA; + LPC_SC->PLL0FEED = 0x55; + + LPC_SC->PLL0CON = 0x01; /* PLL0 Enable */ + LPC_SC->PLL0FEED = 0xAA; + LPC_SC->PLL0FEED = 0x55; + while (!(LPC_SC->PLL0STAT & (1<<26)));/* Wait for PLOCK0 */ + + LPC_SC->PLL0CON = 0x03; /* PLL0 Enable & Connect */ + LPC_SC->PLL0FEED = 0xAA; + LPC_SC->PLL0FEED = 0x55; + while ((LPC_SC->PLL0STAT & ((1<<25) | (1<<24))) != ((1<<25) | (1<<24))); /* Wait for PLLC0_STAT & PLLE0_STAT */ +#endif + +#if (PLL1_SETUP) + LPC_SC->PLL1CFG = PLL1CFG_Val; + LPC_SC->PLL1FEED = 0xAA; + LPC_SC->PLL1FEED = 0x55; + + LPC_SC->PLL1CON = 0x01; /* PLL1 Enable */ + LPC_SC->PLL1FEED = 0xAA; + LPC_SC->PLL1FEED = 0x55; + while (!(LPC_SC->PLL1STAT & (1<<10)));/* Wait for PLOCK1 */ + + LPC_SC->PLL1CON = 0x03; /* PLL1 Enable & Connect */ + LPC_SC->PLL1FEED = 0xAA; + LPC_SC->PLL1FEED = 0x55; + while ((LPC_SC->PLL1STAT & ((1<< 9) | (1<< 8))) != ((1<< 9) | (1<< 8))); /* Wait for PLLC1_STAT & PLLE1_STAT */ +#else + LPC_SC->USBCLKCFG = USBCLKCFG_Val; /* Setup USB Clock Divider */ +#endif + + LPC_SC->PCONP = PCONP_Val; /* Power Control for Peripherals */ + + LPC_SC->CLKOUTCFG = CLKOUTCFG_Val; /* Clock Output Configuration */ +#endif + +#if (FLASH_SETUP == 1) /* Flash Accelerator Setup */ + LPC_SC->FLASHCFG = (LPC_SC->FLASHCFG & ~0x0000F000) | FLASHCFG_Val; +#endif +} + +/** + * @} + */ + +/** + * @} + */ diff --git a/F2024/coe718/labs/lab1/Boards/Keil/MCB1700/Blinky_ULp/RTE/_Instruction_Trace/RTE_Components.h b/F2024/coe718/labs/lab1/Boards/Keil/MCB1700/Blinky_ULp/RTE/_Instruction_Trace/RTE_Components.h new file mode 100755 index 0000000..22becf2 --- /dev/null +++ b/F2024/coe718/labs/lab1/Boards/Keil/MCB1700/Blinky_ULp/RTE/_Instruction_Trace/RTE_Components.h @@ -0,0 +1,26 @@ + +/* + * Auto generated Run-Time-Environment Configuration File + * *** Do not modify ! *** + * + * Project: 'Blinky' + * Target: 'Instruction Trace' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "LPC17xx.h" + +/* Keil.ARM Compiler::Compiler:I/O:STDOUT:ITM:1.2.0 */ +#define RTE_Compiler_IO_STDOUT /* Compiler I/O: STDOUT */ + #define RTE_Compiler_IO_STDOUT_ITM /* Compiler I/O: STDOUT ITM */ +/* Keil::Device:Startup:1.0.0 */ +#define RTE_DEVICE_STARTUP_LPC17XX /* Device Startup for NXP17XX */ + + +#endif /* RTE_COMPONENTS_H */ diff --git a/F2024/coe718/labs/lab1/Boards/Keil/MCB1700/Blinky_ULp/RTE/_SWO_Trace/RTE_Components.h b/F2024/coe718/labs/lab1/Boards/Keil/MCB1700/Blinky_ULp/RTE/_SWO_Trace/RTE_Components.h new file mode 100755 index 0000000..4a59c64 --- /dev/null +++ b/F2024/coe718/labs/lab1/Boards/Keil/MCB1700/Blinky_ULp/RTE/_SWO_Trace/RTE_Components.h @@ -0,0 +1,26 @@ + +/* + * Auto generated Run-Time-Environment Configuration File + * *** Do not modify ! *** + * + * Project: 'Blinky' + * Target: 'SWO Trace' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "LPC17xx.h" + +/* Keil.ARM Compiler::Compiler:I/O:STDOUT:ITM:1.2.0 */ +#define RTE_Compiler_IO_STDOUT /* Compiler I/O: STDOUT */ + #define RTE_Compiler_IO_STDOUT_ITM /* Compiler I/O: STDOUT ITM */ +/* Keil::Device:Startup:1.0.0 */ +#define RTE_DEVICE_STARTUP_LPC17XX /* Device Startup for NXP17XX */ + + +#endif /* RTE_COMPONENTS_H */ diff --git a/F2024/coe718/labs/lab1/Boards/Keil/MCB1700/Blinky_ULp/RTE/_TracePort_Trace/RTE_Components.h b/F2024/coe718/labs/lab1/Boards/Keil/MCB1700/Blinky_ULp/RTE/_TracePort_Trace/RTE_Components.h new file mode 100755 index 0000000..16647d9 --- /dev/null +++ b/F2024/coe718/labs/lab1/Boards/Keil/MCB1700/Blinky_ULp/RTE/_TracePort_Trace/RTE_Components.h @@ -0,0 +1,26 @@ + +/* + * Auto generated Run-Time-Environment Configuration File + * *** Do not modify ! *** + * + * Project: 'Blinky' + * Target: 'TracePort Trace' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "LPC17xx.h" + +/* Keil.ARM Compiler::Compiler:I/O:STDOUT:ITM:1.2.0 */ +#define RTE_Compiler_IO_STDOUT /* Compiler I/O: STDOUT */ + #define RTE_Compiler_IO_STDOUT_ITM /* Compiler I/O: STDOUT ITM */ +/* Keil::Device:Startup:1.0.0 */ +#define RTE_DEVICE_STARTUP_LPC17XX /* Device Startup for NXP17XX */ + + +#endif /* RTE_COMPONENTS_H */ |